One of the simplest phase comparators can be termed a two-state device in that it adopts one output logic state when one input transition occurs, and it adopts the other output logic state when the other input transition occurs. Such a phase comparator is capable of exhibiting good linearity over one cycle of phase difference, but once the phase of either signal differs by more than a half cycle from lock, the absolute phase information is lost. For most applications a two-state phase comparator has an unusable capture performance.
A three-state phase comparator, has a wide capture range, but it suffers from output non-linearity when the two input signals are in lock or nearly so, and it is at just this point that the most predictable and stable output signal is generally needed for control purposes.
A four or higher state phase comparator is capable of providing a wide capture range, but such a device has proved very difficult to implement in a practical manner without resulting in a very complex arrangement which is susceptible to race problems which is operable only at relatively low frequencies. Race problems occur when sequences of events cause logic signal intervals at the comparator to occur out of the correct order or in an unpredictable manner, giving rise to incorrect results or an unusable output signal.